Note: pictures of schemes in good quality can be found in the section Downloads/Electronic Devices
 

Once I worked as a programmer in a small private company, where in addition to a devices of regular complexity, got the task of the voice channels mixer "revival" (further Audio Conferencing Device). By the company stories they has spent more than 2 years and sizable funds for the schematics development and manufacturing of PCBs for a set of a dozen devices. "Fortunately" I had to begin with the development of a dedicated fast boot-loader for MCU S3F441FX via UART port, because the company did not have any debugging tools. Productivity of loader created by previous developers was, for example 7Kb image within ten (10!) minutes, but via JTAG port.

CPU Loader1

The following figure shows settings of PC COM-port through which the loader communicating:

CPU Loader2

Device Parts

The design of the device motherboard was quite surprising. For example, the length of 16 MHz clock frequency line was about 40 cm and pass through several connectors, not suitable for such a device and mounted on the main board in unexpected manner (horizontal).

MBT

Also, I had filling that some FPGAs added to the board without a prior determination of their purpose. A sort of "black boxes", passes through all available signals, so if necessary, be able to execute any electronics scheme inside them (see. the figure below). At the same time, specialized pins of fast spread signals of FPGA was often used for inappropriate purposes, which makes development sometimes quite difficult.

cof

But finally, the device got "breath" and even became successful selling. Thus, the complete list of the device's software parts is:

  1. Main board:
    MCU ARM-7 (S3F441FX)
    DSP DELIC (PEB20571)
    FPGA Altera
  2. Cofidec board:
    FPGA Altera
    Cofidec (TP3070V)
  3. Personal Computer:
    GUI software to control conferences and testing and debugging of the device (MS Windows)
    Help on demand explaining PC GUI
    MCU S3F441FX loader (MS Windows)

After the project completion I left that company, but at the end proposed the scheme, which presenting here. Definitely, my sheme is not that amazing as the next one:

circuit diagram

(c) Rundall Munroe xkcd.com

But I was trying to do my best. It contains the only one FPGA, and additionally intended to support E1 via FALC56 (PEF2256H) framer. Notice, because the company had no special equipment for debugging of such purpose devices, I did not work with framer and did not switch to another MCU. The project is quite big, so I describing it in a very abbreviated form.

Note: PC's side software GUI has Russian language, but hope that icons will help to understand it.